specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. o0610 sy/33110 sy no.a1693-1/8 LV5233H overview the LV5233H is a semiconductor integrated circuit that incorporates a serial input and serial or parallel output 24-stage shift register that features a cmos structure based on bi-cmos process technology. the LV5233H also contains an n-channel cmos construction high-withstand-voltage, la rge-current drive 24-stage parallel output driver. the protection circuit of the output malfunction is built into. features ? serial input and serial or parallel output ? enable input for output control ? serial output enables cascade connection ? low supply current (0.45ma typ. during standby icc 0.6ma) ? serial input/output levels compatible with typical cmos devices ? high-withstand-voltage led driver with open drain output high withstand voltage (vds < 42v) high-current drive (i o max = 100ma) ? operating temperature range ta = -25 to 75 c ? output malfunction protection circuit reset input pin thermal protection circuit v cc decrease voltage confirmation specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max sv cc 6v output voltage v o max ledo1 to ledo24 off 42 v output current i o max 100 ma allowable power dissipation pd max ta 25 c * 1750 mw operating temperature topr -25 to +75 c storage temperature tstg -40 to +125 c * specified board : 114.3mm 76.1mm 1.6mm, glass epoxy board. bi-cmos ic 24ch led driver orderin g numbe r : en*a1693a
LV5233H no.a1693-2/8 operating conditions at ta = 25 c parameter symbol conditions ratings unit recommended supply voltage v cc sv cc 5.0 v operating supply voltage range v cc op sv cc 3.0 to 5.5 v output applied voltage v o 42 v output current i o duty = 45% to 55% 100 ma electrical characteristics at ta = 25 c, v cc = 5.0v ratings parameter symbol conditions min typ max unit quiescent current drain i cc 1 ledo driver off (standby) 0.45 0.6 ma ledo output on resistance ron i o = 30ma 3 off leak current ileak v o = 42v 0 10 a driver output malfunction prevention voltage vt 2.58 2.70 2.82 v control circuit block h level 1 v in h1 input h level v cc 0.8 v l level 1 v in l1 input l level 0 v cc 0.2 v h level 2 v o uth1 sout i o = -1ma v cc -0.3 v l level 2 v o utl1 sout i o = 1ma 0 0.3 v package dimensions unit : mm (typ) 3235a pin assignment ambient temperature , ta -- c allowable power dissipation, pd max -- w pd max -- ta 0 0.87 1.0 0.5 2.0 --25 75 25 50 0 100 1.5 specified board : 114.3 76.1 1.6mm 3 glass epoxy sanyo : hsop36(375mil) (6.2) 36 1 0.8 17.8 2.7 0.3 (4.9) 10.5 0.65 0.25 (0.5) 7.9 (2.25) 2.45max 0.1 2.0 34 4 sv cc xen 32 5 sout latch 31 6 ledo5 ledo8 29 8 ledo3 ledo10 26 11 ledo2 ledo11 24 13 ledo1 ledo12 23 14 sdatain sck 21 16 xreset sgnd top view pgnd1 pgnd2 33 35 36 3 2 1 15 17 18 22 20 19 ledo13 ledo14 pgnd3 ledo15 ledo17 ledo20 ledo22 pgnd4 ledo23 ledo24 heat sink &gnd heat sink &gnd ledo9 7 ledo7 9 ledo6 10 ledo4 12 30 ledo16 28 ledo18 27 ledo19 25 ledo21
LV5233H no.a1693-3/8 pin descriptions pin no. pin name i/o description 1 sv cc power supply 2 sout o shift register output (final-stage shift register) 3 ledo12 o ledo12 latch output (ledo12 of shift register) 4 ledo11 o ledo11 latch output (ledo11 of shift register) 5 ledo10 o ledo10 latch output (ledo10 of shift register) 6 pgnd2 gnd 7 ledo9 o ledo9 latch output (ledo9 of shift register) 8 ledo8 o ledo8 latch output (ledo8 of shift register) 9 ledo7 o ledo7 latch output (ledo7 of shift register) heat sink 10 ledo6 o ledo6 latch output (ledo6 of shift register) 11 ledo5 o ledo5 latch output (ledo5 of shift register) 12 ledo4 o ledo4 latch output (ledo4 of shift register) 13 pgnd1 gnd 14 ledo3 o ledo3 latch output (ledo3 of shift register) 15 ledo2 o ledo2 latch output (ledo2 of shift register) 16 ledo1 o ledo1 latch output (ledo1 of shift register) 17 sdatain i serial input 18 xreset i reset input (shift register and latch) 19 sgnd gnd 20 sck i clock input (for shift register) 21 ledo24 o ledo24 latch output (ledo24 of shift register) 22 ledo23 o ledo23 latch output (ledo23 of shift register) 23 ledo22 o ledo22 latch output (ledo22 of shift register) 24 pgnd4 gnd 25 ledo21 o ledo21 latch output (ledo21 of shift register) 26 ledo20 o ledo20 latch output (ledo20 of shift register) 27 ledo19 o ledo19 latch output (ledo19 of shift register) heat sink 28 ledo18 o ledo18 latch output (ledo18 of shift register) 29 ledo17 o ledo17 latch output (ledo17 of shift register) 30 ledo16 o ledo16 latch output (ledo16 of shift register) 31 pgnd3 gnd 32 ledo15 o ledo15 latch output (ledo15 of shift register) 33 ledo14 o ledo14 latch output (ledo14 of shift register) 34 ledo13 o ledo13 latch output (ledo13 of shift register) 35 latch i latch input when the latch input is held low, the led0 output status is retained. when a high-level is input, the led0 outputs change when the status of the shift register changes. 36 xen i enable inputs (ledo1 to ledo24) when a high-level is input, all the led0 outputs are turned off. when a low-level is input, the shift register data is output to led0.
LV5233H no.a1693-4/8 block diagram function the LV5233H consists of 1) an 24-stage d-type flip-flop and 2) an 24-stage d-type flip-flop connected to the output of 1). when data is supplied to the serial data input (sdatain) and the clock puls e is supplied to the clock input (sck), the serial data input signal is input to the internal shift register and the data already in the shift register shifted sequentially when the clock changes from low to high. the serial output (sout) is used to co nnect multiple LV5233H to expand the number of bits and is connected to the sdatain of the next stage. (cascade connection supported.) for parallel output, when the output control enable input (xen ) is low, the latch input (latch) changes from low to high and the clock pulse input changes from low to high, the serial data input signal is output to led01, and the output is shifted sequentially. for parallel output s (led2 to led24), the signals whose polarities inverted from those of the serial data input (sdatain) are output. when the en input is high, outputs led01 through led01 all turn off. when the reset input is low, outputs led01 through led24 and sout outputs all turn off. the power must be turned on after checking that the reset input is low. to prevent the malfunction, the output load protection circuit is built into. the output of ledo1 to ledo24 is compulsorily turned off when becoming below the voltage with a constant there is v cc . moreover, a thermal circuit is built into, and the output of ledo1 to ledo24 is turned off compulsorily when becoming it at the temperature that exceeds the temperature of the junction in ic. xreset sv cc xen sout sgnd pgnd1 pgnd2 latch sdatain sck ledo1 dq c r q dq c r q dq c r q dq c r q dq c r q dq c r q dq c r q dq c r q dq c r q dq c r q dq c r q dq c r q dq c r q ledo2 ledo3 ledo22 ledo23 ledo24 sv cc _protection pgnd3 pgnd4 ledo4 ledo21
LV5233H no.a1693-5/8 pin functions pin no. pin name pin function equivalent circuit 17 20 sdatain sck pull-down input sv cc sgnd 18 35 36 xreset latch xen pull-up input sv cc sgnd 2 sout sout output sv cc sgnd sout 3 4 5 7 8 9 10 11 12 14 15 16 21 22 23 25 26 27 28 29 30 32 33 34 ledo12 ledo11 ledo10 ledo9 ledo8 ledo7 ledo6 ledo5 ledo4 ledo3 ledo2 ledo1 ledo24 ledo23 ledo22 ledo21 ledo20 ledo19 ledo18 ledo17 ledo16 ledo15 ledo14 ledo13 ledo outputs ledo1 to ledo24 sv cc sgnd pgnd
LV5233H no.a1693-6/8 timing conditions parameter symbol conditions min typ max unit clock frequency fs1 sck duty = 50% 10 mhz clock pulse width twck sck 50 ns latch pulse width twla latch 50 ns data set up time ts1 sdatain setup time relative to the rise of sck 25 ns data hold time th1 sdatain data hold time relative to the rise of sck 25 ns clock latch time tla1 100 ns input conditions 1 ton sck and sdatain rise time 100 ns input conditions 2 toff scl and sdatain fall time 100 ns sout output timings parameter symbol conditions min typ max unit sout delay time 1 tdso1 the time from a sck falling edge to sout rising edge 50 ns sout delay time 2 tdso2 the time from a sck falling edge to sout falling edge 50 ns 2.5v 2.5v sck sdatain latch 2.5v 2.5v ts1 10% 90% 10% 90% th1 2.5v 2.5v tla1 twla toff ton twck 2.5v sck sout 2.5v 2.5v tdso1 2.5v tdso2
LV5233H no.a1693-7/8 ledo output timings parameter symbol conditions min typ max unit ledo delay time 1 tdled1 the time from an xen rising edge to ledo rising edge cl = 30pf, i o = 100ma, v o = 42v 100 ns ledo delay time 2 tdled2 the time from an xen falling edge to ledo falling edge cl = 30pf, i o = 100ma, v o = 42v 100 ns ledo rise time trled ledo rise time cl = 30pf, i o = 100ma, v o = 42v 200 ns ledo fall time tfled ledo fall time cl = 30pf, i o = 100ma, v o = 42v 200 ns ledo delay time 3 tdled3 the time from a latch rising edge to ledo falling edge cl = 30pf, i o = 100ma, v o = 42v 200 ns application circuit example latch ledo 2.5v 2.5v xen 2.5v tdled1 10% 90% 10% 90% tdled3 90% trled tfled tdled2 ledo ledo sout max:42v sdatain sv cc sgnd pgnd 5v sck latch xen xreset ledo ledo sout sdatain sv cc sgnd pgnd sck latch xen xreset sub cpu
LV5233H ps no.a1693-8/8 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. allowable output current characteristics this catalog provides information as of october, 2010. specifications and information herein are subject to change without notice. 90 70 80 2 8 12 14 46 10 i o -- ledo 60 100 016 ta = 25 c 50 c 75 c output current, i o - ma number of output ports, ledo duty syscle 100%
|
